This book presents the different challenges of secure processor architecture design for architects working in industry who want to add security features to their designs as well as graduate students interested in research on architecture and hardware security. It educates readers about how the different challenges have been solved in the past and what are the best practices, i.e., the principles, for design of new secure processor architectures. Based on the careful review of past work by many computer architects and security researchers, readers also will come to know the five basic principles needed for secure processor architecture design. The book also presents existing research challenges and potential new research directions. Finally, it presents numerous design suggestions, as well as discussing pitfalls and fallacies that designers should avoid. With growing interest in computer security and the protection of the code and data which execute on commodity computers, the amount of hardware security features in today's processors has increased significantly over the recent years. No longer of just academic interest, security features inside processors have been embraced by industry as well, with a number of commercial secure processor architectures available today. This book gives readers insights into the principles behind the design of academic and commercial secure processor architectures. Secure processor architecture research is concerned with exploring and designing hardware features inside computer processors, features which can help protect confidentiality and integrity of the code and data executing on the processor. Unlike traditional processor architecture research that focuses on performance, efficiency, and energy as the first-order design objectives, secure processor architecture design has security as the first-order design objective (while still keeping the others as important design aspects that need to be considered).

As Moore's Law and Dennard scaling trends have slowed, the challenges of building high-performance computer architectures while maintaining acceptable power efficiency levels have heightened. Over the past ten years, architecture techniques for power efficiency have shifted from primarily focusing on module-level efficiencies, toward more holistic design styles based on parallelism and heterogeneity. This work highlights and synthesizes recent techniques and trends in power-efficient computer architecture. Table of Contents: Introduction / Voltage and Frequency Management / Heterogeneity and Specialization / Communication and Memory Systems / Conclusions / Bibliography / Authors' Biographies

HiPEAC2009wasthe fourthedition ofthe HiPEACconferenceseries.This c- ferenceseriesislargelyassociatedwiththeFP7NetworkofExcellenceHiPEAC2. The ?rst three editions of the conference in Barcelona (2005), Ghent (2007) and G] oteborg (2008) attracted a lot of interest with more than 200 attendees at the last two editions and satellite events. It is a great privilege for us to welcome you to the fourth HiPEAC conference in the beautiful, touristic city of Paphos, Cyprus. The o?erings of this conference are rich and diverse. We o?er attendees a set of seven workshopson topics that are central to the HiPEAC network roadmap: multi-cores, simulation and performance evaluation, compiler optimizations, - sign reliability, recon?gurable computing, and interconnection networks. Ad- tionally, a tutorial on design reliability is o?ered. Theconferenceprogramwasasrichaslastyear's.Itfeaturedmanyimportant andtimelytopicssuchasmulti-coreprocessors, recon?gurablesystems, compiler optimization, power-awaretechniquesand more.The conferencealso o?ered two keynote speeches: Tilak Agerwala from IBM Research presenting the view from a major industry player, and Fran, cois Bodin from CAPS-Entreprise presenting the view of a start-up. There were several social activities during the conference o?ering ample - portunity for informal interaction. These included a reception, an excursion to various archeological sites and a banquet at a traditional tavern. Thisyearwereceived97papersubmissions, ofwhich14wereco-authoredbya Program Committee member. Papers were submitted from 20 di?erent nations (approximately 46% from Europe, 15% from Asia, 32% from North America, 4% from Africa and the Middle East, and 3% from South America), which is an indicator of the global visibility of the conference."

In the last few years, power dissipation has become an important design constraint, on par with performance, in the design of new computer systems. Whereas in the past, the primary job of the computer architect was to translate improvements in operating frequency and transistor count into performance, now power efficiency must be taken into account at every step of the design process. While for some time, architects have been successful in delivering 40% to 50% annual improvement in processor performance, costs that were previously brushed aside eventually caught up. The most critical of these costs is the inexorable increase in power dissipation and power density in processors. Power dissipation issues have catalyzed new topic areas in computer architecture, resulting in a substantial body of work on more power-efficient architectures. Power dissipation coupled with diminishing performance gains, was also the main cause for the switch from single-core to multi-core architectures and a slowdown in frequency increase. This book aims to document some of the most important architectural techniques that were invented, proposed, and applied to reduce both dynamic power and static power dissipation in processors and memory hierarchies. A significant number of techniques have been proposed for a wide range of situations and this book synthesizes those techniques by focusing on their common characteristics. Table of Contents: Introduction / Modeling, Simulation, and Measurement / Using Voltage and Frequency Adjustments to Manage Dynamic Power / Optimizing Capacitance and Switching Activity to Reduce Dynamic Power / Managing Static (Leakage) Power / Conclusions